SELCC=CHANNEL_0_RISING_EDG, CINSEL=CHANNEL_0, CTMODE=TIMER_MODE
Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
| CTMODE | Counter/Timer Mode This field selects which rising PCLK edges can increment Timer’s Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. 0 (TIMER_MODE): Timer Mode. Incremented every rising PCLK edge. 1 (COUNTER_MODE_RISING): Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. 2 (COUNTER_MODE_FALLING): Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. 3 (COUNTER_MODE_DUAL_ED): Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. |
| CINSEL | Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. 0 (CHANNEL_0): Channel 0. CAPn.0 for TIMERn 1 (CHANNEL_1): Channel 1. CAPn.1 for TIMERn 2 (CHANNEL_2): Channel 2. CAPn.2 for TIMERn 3 (CHANNEL_3): Channel 3. CAPn.3 for TIMERn |
| ENCC | Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. |
| SELCC | Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved. 0 (CHANNEL_0_RISING_EDG): Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). 1 (CHANNEL_0_FALLING_ED): Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). 2 (CHANNEL_1_RISING_EDG): Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). 3 (CHANNEL_1_FALLING_ED): Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). 4 (CHANNEL_2_RISING_EDG): Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). 5 (CHANNEL_2_FALLING_ED): Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |